Multi-Threshold Based Low Power Dual Edge Triggered Flip-Flop
نویسندگان
چکیده
Digital circuit design is streamlined process used to improve the performance of a circuit for a particular application. Fast speed, minimum power dissipation and less area are the desirable characteristics of a digital circuit, in general. To meet a particular standard of speed, a compromise in power dissipation and speed is required. Timing elements such as Flip-flop are used as clock generators. These consume almost 50% of the total system power. In this paper, a low power dual edge triggered D flip-flop is proposed. The circuit complexity is reduced by using less number of transistors. Multi-threshold technique is employed to reduce the power dissipation of the proposed circuit.
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